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IT Support & Hardware · Intermediate

PCIe Lanes

Individual full-duplex serial links that make up a PCIe connection; more lanes provide more bandwidth.

Definition

Each lane is a pair of differential signal pairs (transmit and receive). CPUs and chipsets have a limited lane budget, so populating some M.2 or PCIe slots can disable or reduce other slots. Motherboard manuals list these lane-sharing rules.

Example

Installing an SSD in the second M.2 slot disables SATA ports 5 and 6 on some boards.

Exam tip

Disappearing SATA drives after adding an M.2 SSD is a lane-sharing clue; check the manual.

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